Chip Fast

Design chips for free.

Write a circuit. See it placed and routed. On your laptop.

WHAT IT DOES

Spectral placement: 40M gates in 4.5 seconds
Wire length reduction vs random placement
Row legalization with no gate overlap
Manhattan routing estimation with congestion detection
Missing connection detection (what WANTS to connect)
Netlist parser: paste Verilog-style netlists directly

96% cheaper than Cadence. Runs on a $500 Mac Mini. No license server.

TRY IT

LIVE DEMO

Sample: 500-gate benchmark circuit

$499/mo/mo

Replaces: Cadence Innovus ($750K-2M/yr), Synopsys ICC2 ($500K+/yr)

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